hardware.h File Reference

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Macros
#define	HW_REG(reg, type)   *(volatile type *)(reg | 0xa0000000)
#define	AI_DRAM_ADDR_REG   0x04500000
#define	AI_LEN_REG   0x04500004
#define	AI_CONTROL_REG   0x04500008
#define	AI_STATUS_REG   0x0450000C
#define	AI_STATUS_AI_FULL   (1 << 31)
#define	AI_STATUS_AI_BUSY   (1 << 30)
#define	AI_DACRATE_REG   0x04500010
#define	AI_BITRATE_REG   0x04500014
#define	VI_STATUS_REG   0x04400000
#define	VI_CONTROL_REG   0x04400000
#define	VI_ORIGIN_REG   0x04400004
#define	VI_DRAM_ADDR_REG   0x04400004
#define	VI_WIDTH_REG   0x04400008
#define	VI_H_WIDTH_REG   0x04400008
#define	VI_INTR_REG   0x0440000C
#define	VI_V_INTER_REG   0x0440000C
#define	VI_CURRENT_REG   0x04400010
#define	VI_V_CURRENT_LINE_REG   0x04400010
#define	VI_BURST_REG   0x04400014
#define	VI_TIMING_REG   0x04400014
#define	VI_V_SYNC_REG   0x04400018
#define	VI_H_SYNC_REG   0x0440001C
#define	VI_LEAP_REG   0x04400020
#define	VI_H_SYNC_LEAP_REG   0x04400020
#define	VI_H_START_REG   0x04400024
#define	VI_H_VIDEO_REG   0x04400024
#define	VI_V_START_REG   0x04400028
#define	VI_V_VIDEO_REG   0x04400028
#define	VI_V_BURST_REG   0x0440002C
#define	VI_X_SCALE_REG   0x04400030
#define	VI_Y_SCALE_REG   0x04400034
#define	SP_IMEM_START   0x04001000
#define	SP_DMEM_START   0x04000000
#define	SP_MEM_ADDR_REG   0x04040000
#define	SP_DRAM_ADDR_REG   0x04040004
#define	SP_RD_LEN_REG   0x04040008
#define	SP_WR_LEN_REG   0x0404000C
#define	SP_STATUS_REG   0x04040010
#define	SP_PC_REG   0x04080000
#define	PI_DRAM_ADDR_REG   0x04600000
#define	PI_CART_ADDR_REG   0x04600004
#define	PI_RD_LEN_REG   0x04600008
#define	PI_WR_LEN_REG   0x0460000C
#define	PI_STATUS_REG   0x04600010
#define	PI_BSD_DOM1_LAT_REG   0x04600014
#define	PI_DOMAIN1_REG   0x04600014
#define	PI_BSD_DOM1_PWD_REG   0x04600018
#define	PI_BSD_DOM1_PGS_REG   0x0460001C
#define	PI_BSD_DOM1_RLS_REG   0x04600020
#define	PI_BSD_DOM2_LAT_REG   0x04600024
#define	PI_DOMAIN2_REG   0x04600024
#define	PI_BSD_DOM2_PWD_REG   0x04600028
#define	PI_BSD_DOM2_PGS_REG   0x0460002C
#define	PI_BSD_DOM2_RLS_REG   0x04600030
#define	PI_STATUS_BUSY   0x1
#define	PI_STATUS_IOBUSY   0x2
#define	PI_STATUS_ERROR   0x3
#define	SI_DRAM_ADDR_REG   0x04800000
#define	SI_PIF_ADDR_RD64B_REG   0x04800004
#define	SI_PIF_ADDR_WR64B_REG   0x04800010
#define	SI_STATUS_REG   0x04800018
#define	SI_STATUS_DMA_BUSY   0x1
#define	SI_STATUS_IO_READ_BUSY   0x2
#define	SI_STATUS_DMA_ERROR   0x8
#define	SI_STATUS_INTERRUPT   (1 << 12)
#define	MI_INIT_MODE_REG   0x04300000
#define	MI_MODE_REG   MI_INIT_MODE_REG
#define	MI_VERSION_REG   0x04300004
#define	MI_INTR_REG   0x04300008
#define	MI_INTR_MASK_REG   0x0430000C

Macro Definition Documentation

AI_BITRATE_REG

#define AI_BITRATE_REG   0x04500014

AI_CONTROL_REG

#define AI_CONTROL_REG   0x04500008

AI_DACRATE_REG

#define AI_DACRATE_REG   0x04500010

AI_DRAM_ADDR_REG

#define AI_DRAM_ADDR_REG   0x04500000

AI_LEN_REG

#define AI_LEN_REG   0x04500004

AI_STATUS_AI_BUSY

#define AI_STATUS_AI_BUSY   (1 << 30)

AI_STATUS_AI_FULL

#define AI_STATUS_AI_FULL   (1 << 31)

AI_STATUS_REG

#define AI_STATUS_REG   0x0450000C

HW_REG

#define HW_REG	(		reg,
			type
	)		*(volatile type *)(reg | 0xa0000000)

MI_INIT_MODE_REG

#define MI_INIT_MODE_REG   0x04300000

MI_INTR_MASK_REG

#define MI_INTR_MASK_REG   0x0430000C

MI_INTR_REG

#define MI_INTR_REG   0x04300008

MI_MODE_REG

#define MI_MODE_REG   MI_INIT_MODE_REG

MI_VERSION_REG

#define MI_VERSION_REG   0x04300004

PI_BSD_DOM1_LAT_REG

#define PI_BSD_DOM1_LAT_REG   0x04600014

PI_BSD_DOM1_PGS_REG

#define PI_BSD_DOM1_PGS_REG   0x0460001C

PI_BSD_DOM1_PWD_REG

#define PI_BSD_DOM1_PWD_REG   0x04600018

PI_BSD_DOM1_RLS_REG

#define PI_BSD_DOM1_RLS_REG   0x04600020

PI_BSD_DOM2_LAT_REG

#define PI_BSD_DOM2_LAT_REG   0x04600024

PI_BSD_DOM2_PGS_REG

#define PI_BSD_DOM2_PGS_REG   0x0460002C

PI_BSD_DOM2_PWD_REG

#define PI_BSD_DOM2_PWD_REG   0x04600028

PI_BSD_DOM2_RLS_REG

#define PI_BSD_DOM2_RLS_REG   0x04600030

PI_CART_ADDR_REG

#define PI_CART_ADDR_REG   0x04600004

PI_DOMAIN1_REG

#define PI_DOMAIN1_REG   0x04600014

PI_DOMAIN2_REG

#define PI_DOMAIN2_REG   0x04600024

PI_DRAM_ADDR_REG

#define PI_DRAM_ADDR_REG   0x04600000

PI_RD_LEN_REG

#define PI_RD_LEN_REG   0x04600008

PI_STATUS_BUSY

#define PI_STATUS_BUSY   0x1

PI_STATUS_ERROR

#define PI_STATUS_ERROR   0x3

PI_STATUS_IOBUSY

#define PI_STATUS_IOBUSY   0x2

PI_STATUS_REG

#define PI_STATUS_REG   0x04600010

PI_WR_LEN_REG

#define PI_WR_LEN_REG   0x0460000C

SI_DRAM_ADDR_REG

#define SI_DRAM_ADDR_REG   0x04800000

SI_PIF_ADDR_RD64B_REG

#define SI_PIF_ADDR_RD64B_REG   0x04800004

SI_PIF_ADDR_WR64B_REG

#define SI_PIF_ADDR_WR64B_REG   0x04800010

SI_STATUS_DMA_BUSY

#define SI_STATUS_DMA_BUSY   0x1

SI_STATUS_DMA_ERROR

#define SI_STATUS_DMA_ERROR   0x8

SI_STATUS_INTERRUPT

#define SI_STATUS_INTERRUPT   (1 << 12)

SI_STATUS_IO_READ_BUSY

#define SI_STATUS_IO_READ_BUSY   0x2

SI_STATUS_REG

#define SI_STATUS_REG   0x04800018

SP_DMEM_START

#define SP_DMEM_START   0x04000000

SP_DRAM_ADDR_REG

#define SP_DRAM_ADDR_REG   0x04040004

SP_IMEM_START

#define SP_IMEM_START   0x04001000

SP_MEM_ADDR_REG

#define SP_MEM_ADDR_REG   0x04040000

SP_PC_REG

#define SP_PC_REG   0x04080000

SP_RD_LEN_REG

#define SP_RD_LEN_REG   0x04040008

SP_STATUS_REG

#define SP_STATUS_REG   0x04040010

SP_WR_LEN_REG

#define SP_WR_LEN_REG   0x0404000C

VI_BURST_REG

#define VI_BURST_REG   0x04400014

VI_CONTROL_REG

#define VI_CONTROL_REG   0x04400000

VI_CURRENT_REG

#define VI_CURRENT_REG   0x04400010

VI_DRAM_ADDR_REG

#define VI_DRAM_ADDR_REG   0x04400004

VI_H_START_REG

#define VI_H_START_REG   0x04400024

VI_H_SYNC_LEAP_REG

#define VI_H_SYNC_LEAP_REG   0x04400020

VI_H_SYNC_REG

#define VI_H_SYNC_REG   0x0440001C

VI_H_VIDEO_REG

#define VI_H_VIDEO_REG   0x04400024

VI_H_WIDTH_REG

#define VI_H_WIDTH_REG   0x04400008

VI_INTR_REG

#define VI_INTR_REG   0x0440000C

VI_LEAP_REG

#define VI_LEAP_REG   0x04400020

VI_ORIGIN_REG

#define VI_ORIGIN_REG   0x04400004

VI_STATUS_REG

#define VI_STATUS_REG   0x04400000

VI_TIMING_REG

#define VI_TIMING_REG   0x04400014

VI_V_BURST_REG

#define VI_V_BURST_REG   0x0440002C

VI_V_CURRENT_LINE_REG

#define VI_V_CURRENT_LINE_REG   0x04400010

VI_V_INTER_REG

#define VI_V_INTER_REG   0x0440000C

VI_V_START_REG

#define VI_V_START_REG   0x04400028

VI_V_SYNC_REG

#define VI_V_SYNC_REG   0x04400018

VI_V_VIDEO_REG

#define VI_V_VIDEO_REG   0x04400028

VI_WIDTH_REG

#define VI_WIDTH_REG   0x04400008

VI_X_SCALE_REG

#define VI_X_SCALE_REG   0x04400030

VI_Y_SCALE_REG

#define VI_Y_SCALE_REG   0x04400034